A magnetic memory cell or device, such as a magnetoresistive random access memory (MRAM) device stores information by changing electrical resistance of a magnetic tunnel junction (MTJ) element. The MTJ element typically includes a thin insulating tunnel barrier layer sandwiched between a magnetically fixed layer and a magnetically free layer, forming a magnetic tunnel junction. The MTJ element could be formed of either a bottom pinned MTJ element or a top pinned MTJ element. The bottom pinned MTJ element is formed by having the magnetically fixed layer disposed below the magnetically free layer while the top pinned MTJ element is formed by having the fixed layer disposed above the free layer.
Spin transfer torque (STT) or spin transfer switching, uses spin-aligned (“polarized”) electrons to directly apply a torque on the MTJ layers. Specifically, when electrons flowing into a layer have to change spin direction, a torque is developed and is transferred to the nearby layer. Data is written by altering the magnetic field direction of a magnetically free layer in the MTJ element. This affects the resistance of the structure, thereby storing the written data.
MRAM devices contain elements, or cells, that switch the MRAM device between a first state and a second state. With current methods for switching an MRAM device from a first state to a second state, write failure occurs due to several possible mechanisms, including distributions of write currents in an ensemble of bits or nondeterministic switching due to the specific nature of the write method used. In the former case, writing may be mostly successful but once in a while a write error will occur. The latter case, which is typically referred to as probabilistic switching, makes writing strongly dependent on certain parameters, such as the width of the write voltage/current pulse. While write errors can be mitigated by adding error correction code (ECC), this method adds complexity and cost to the building of memory chips. The use of ECC requires the final state be measured and the write procedure repeated if the device is not in the desired state. This method significantly degrades memory latency because it is time consuming and is not optimal as there is still a non-zero probability for the device to end up in the wrong state even after a large number of tries.
In order to achieve a low bit error rate (BER) for switching processes, faster switching performance, and greater barrier reliability, efforts have been made to reduce the MRAM switching voltage. Typically, these efforts have focused on fabricating the most robust MTJ material stack. However, low BER, faster switching performance and greater barrier reliability are among many factors considered during MTJ material stack development. For example, thermal stability, on/off ratio, and switching symmetry are also affected when the MTJ material stack is tuned for reduced voltage switching. These conflicting considerations make the optimization of the MTJ material stack difficult.
In view of the foregoing, it is desirable to provide an MRAM structure with a low bit error rate (BER) for switching processes, faster switching performance, and greater barrier reliability without interfering in the MTJ material stack design. Furthermore, it is also desirable to provide integrated circuits with magnetic field assisted MRAM structures. Also, it is desirable to provide methods for fabricating such integrated circuits that are cost effective and compatible with logic processing. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background.